avalon_slave_waitrequest sys_clk or negedge sys_rst) beginĮlse if (led_counter = 31'd100_000_000) beginĮlse if (led_counter = 31'd200_000_000) begin avalon_slave_readdatavalid (avalon_slave_readdatavalid), avalon_slave_readdata (avalon_slave_readdata), avalon_slave_writedata (avalon_slave_writedata), avalon_slave_byteenable (avalon_slave_byteenable), avalon_slave_address (avalon_slave_address), sobus_byteenable (avalon_slave_byteenable), //. sobus_address (avalon_slave_address), //. sobus_writedata (avalon_slave_writedata), //. sobus_readdatavalid (avalon_slave_readdatavalid), //. sobus_readdata (avalon_slave_readdata), //. sobus_waitrequest (avalon_slave_waitrequest), // sobus.waitrequest

reset_reset_n (sys_rst), // reset.reset_n Reg avalon_slave_address // avalon_slave.address ? The top module is this module FLASH_CTL_TOP ( Reg (posedge clock_sink_clk or negedge reset_sink_reset) beginĪssign avalon_slave_readdata = Īssign debugaccess = (posedge clock_sink_clk or negedge reset_sink_reset)beginĪv_rd_byte1 <= 0 av_rd_byte2 <= 0 av_rd_byte3 <= 0 av_rd_byte4 <= 0 Parameter ST_8 = 4'd8 parameter ST_9 = 4'd9 parameter ST_10 = 4'd10 parameter ST_11 = 4'd11 Parameter ST_4 = 4'd4 parameter ST_5 = 4'd5 parameter ST_6 = 4'd6 parameter ST_7 = 4'd7 Parameter ST_0 = 4'd0 parameter ST_1 = 4'd1 parameter ST_2 = 4'd2 parameter ST_3 = 4'd3 Output wire avalon_slave_waitrequest, //.

Output wire avalon_slave_readdatavalid, //. Input wire clock_sink_clk, // clock_sink_1.clk Input wire reset_sink_reset, // reset_sink.reset I'm adding the code I write for your reference. I'm using a 'testbench-like' module that produce the avalon control, address and data signals like write, read and address, for a future implementation on a larger Avalon communication protocol SoC. I have loaded the system to the board but it is not receiving anything from SO as I thought it would do automatically. I conceived the controller as a finite state machine that suppose to generate the SPI signals in order. I did an effort to produce the SCLK, SI and other signals that the chip needs through verilog, respecting the timing etc. The FPGA chip is Altera 5CEFA4F23C8 and the flash is MX25元206E.

As a school project I want to write a very simple controller for a flash memory in a IC board.

Spi flash verilog